mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 30
![no-image](/images/no-image-200.jpg)
mt46h8m16lfcf-75-it
Manufacturer Part Number
mt46h8m16lfcf-75-it
Description
128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46H8M16LFCF-75-IT.pdf
(84 pages)
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Figure 11:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
WRITE Command
Notes:
DM input logic level appearing coincident with the data. If a given DM signal is regis-
tered LOW, the corresponding data will be written to memory; if the DM signal is regis-
tered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
If a WRITE or a READ is in progress, the entire data burst must be complete prior to stop-
ping the clock (see the “Stopping the External Clock” section on page 81). A burst
completion for WRITEs is defined when the write postamble and
fied.
1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
BA0, BA1
Address
RAS#
CAS#
WE#
CK#
CKE
A10
CS#
CK
HIGH
Column
DIS AP
EN AP
Bank
Don’t Care
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved.
t
WR or
t
WTR are satis-
Commands
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