mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 15

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
128mb_mobile_ddr_sdram_t35m__2.fm - Rev. B 06/08 EN
Parameter
Input capacitance: CK, CK#
Delta input capacitance: CK, CK#
Input capacitance: command and address
Delta input capacitance: command and address
Input/output capacitance: DQs, DQS, DM
Delta input/output capacitance: DQs, DQS, DM
Capacitance (x16, x32)
Note 1 applies to all the parameters in this table
Notes:
Notes:
10. V
11. The value of V
1. All voltages referenced to V
2. All parameters assume proper device initialization.
3. Tests for AC timing, I
4. Outputs measured with equivalent load; transmission line delay is assumed to be very
5. Timing and I
6. Any positive glitch must be less than 1/3 of the clock cycle and not more than +200mV or
7. V
8. To maintain a valid level, the transitioning edge of the input must:
9. V
1. This parameter is sampled. V
2. The input capacitance per pin group will not differ by more than this maximum amount for
3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum
8b. Reach at least the target AC level.
8a. Sustain a constant slew rate from the current AC level through to the target AC level,
8c. After the AC target level is reached, continue to maintain at least the target DC level,
nal supply voltage levels, but the related specifications and device operation are guaran-
teed for the full voltage range specified.
small:
input timing is still referenced to V
timing reference voltage level is V
2.0V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not
exceed either –150mV or +1.6V, whichever is more positive.
be greater than 1/3 of the cycle rate. V
≤3ns and the pulse width cannot be greater than 1/3 of the cycle rate.
CK#.
ations in the DC level of the same.
V
ing the fact that they are matched in loading.
any given device.
amount for any given device.
DD
IH
ID
OUT
I/O
V
V
overshoot: V
is the magnitude of the difference between the input level on CK and the input level on
and V
IL
IL
(
Full drive strength
DC
(
(
AC
DC
z
) = V
0
) or V
) or V
= 50
DD
DD
DD
Q must track each other and V
IX
IH
IH
Q/2, V
tests may use a V
IH
(
(
is expected to equal V
AC
DC
(MAX) = V
).
).
DD
OUT
20pF
, and electrical AC and DC characteristics may be conducted at nomi-
(peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflect-
SS
15
Symbol
DD
DD
.
CDCK
CDIO
I/O
CCK
CDI
CIO
/V
Q + 1.0V for a pulse width ≤3ns and the pulse width cannot
CI
One-half drive strength
IL
DD
-to-V
DD
DD
Q = 1.70–1.95V, f = 100 MHz, T
z
Q/2.
0
Q/2 (or to the crossing point for CK/CK#). The output
= 50
DD
IL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
128Mb: x16, x32 Mobile DDR SDRAM
undershoot: V
Q/2 of the transmitting device and must track vari-
swing of up to 1.5V in the test environment, but
DD
Min
1.5
1.5
2.0
–
–
–
Q must be less than or equal to V
10pF
IL
(MIN) = –1.0V for a pulse width
Max
0.25
3.0
3.0
0.5
4.5
0.5
Electrical Specifications
©2007 Micron Technology, Inc. All rights reserved.
A
= 25°C,
Unit
pF
pF
pF
pF
pF
pF
DD
Preliminary
.
Notes
2
2
3