mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 27

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Commands
Table 14:
Table 15:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER-DOWN
(enter deep power-down mode)
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank) or
SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER
Truth Table – Commands
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences
not shown are reserved and/or illegal
DM Operation Truth Table
Notes:
Notes:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A[0:i] provide row address (where i = the most signifi-
3. BA0–BA1 provide bank address; A[0:i] provide column address (where i = the most signifi-
4. Applies only to READ bursts with auto precharge disabled; this command is undefined and
5. This command is a BURST TERMINATE if CKE is HIGH and DEEP POWER-DOWN if CKE is
6. A10 LOW: BA0–BA1 determine which bank is precharged.
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os are
9. BA0–BA1 select the standard mode register, extended mode register, or status register.
2. All states and sequences not shown are reserved and/or illegal.
Table 14 and Table 15 provide a quick reference of available commands. This is followed
by a written description of each command. Three additional truth tables (Table 16 on
page 34, Table 17 on page 35, and Table 18 on page 37) provide CKE commands and
current/next state information.
1. Used to mask write data; provided coincident with the corresponding data.
Name (Function)
Write enable
Write inhibit
cant address bit for each configuration).
cant address bit for each configuration); A10 HIGH enables the auto precharge feature
(nonpersistent); A10 LOW disables the auto precharge feature.
should not be used for READ bursts with auto precharge enabled and for WRITE bursts.
LOW.
A10 HIGH: all banks are precharged and BA0
“Don’t Care” except for CKE.
27
CS#
H
L
L
L
L
L
L
L
L
DM
H
L
RAS#
X
H
H
H
H
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
L
L
L
128Mb: x16, x32 Mobile DDR SDRAM
–
CAS#
BA1 are “Don’t Care.”
X
H
H
H
H
L
L
L
L
WE#
X
H
H
H
H
Valid
L
L
L
L
DQ
X
©2007 Micron Technology, Inc. All rights reserved.
Bank/column
Bank/column
Bank/row
Address
Op-code
Code
X
X
X
X
Commands
Notes
1, 2
1, 2
Preliminary
Notes
4, 5
7, 8
1
1
2
3
3
6
9