st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 66

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

Interrupts
Caution:
7.6
7.7
Note:
7.7.1
66/371
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Interrupt instructions
Table 19.
1. During the execution of an interrupt routine, the HALT, popCC, RIM, SIM and WFI instructions change the
External interrupts
The pending interrupts are cleared writing a different value in the ISx[1:0], IPA or IPB bits of
the EICR.
External interrupts are masked when an I/O (configured as input interrupt) of the same
interrupt vector is forced to V
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register
interrupt source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3).
HALT
IRET
JRM
JRNM
Pop CC
RIM
SIM
TRAP
WFI
Instruction
current software priority up to the next IRET instruction or one of the previously mentioned instructions.
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
(Figure
Dedicated interrupt instruction set
Entering Halt mode
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Jump if I1:0 <> 11
Pop CC from the stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
Software TRAP
Wait for interrupt
20). This control allows to have up to four fully independent external
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
New description
SS
.
Pop CC, A, X, PC
I1:0 <> 11 ?
Mem => CC
Load 10 in I1:0 of CC
Software NMI
I1:0 = 11 ?
Function/example
(1)
I1
I1
I1
1
1
1
1
1
H
H
H
I0
I0
I0
0
0
1
1
0
N
N
N
Z
Z
Z
C
C
C