st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 364

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

Known limitations
15.4.2
364/371
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Analysis
The LIN protocol specifies a minimum of 13 bits for the break duration, but there is no
maximum value. Nevertheless, the maximum length of the header is specified as
(14 + 10 + 10 + 1) x 1.4 = 49 bits. This is composed of:
Every LIN frame starts with a break character. Adding an idle character increases the length
of each header by 10 bits. When the problem occurs, the header length is increased by 11
bits and becomes ((14 + 11) + 10 + 10 + 1) = 45 bits.
To conclude, the problem is not always critical for LIN communication if the software keeps
the time between the sync field and the ID smaller than 4 bits, that is, 208µs at 19200 baud.
Workaround
The workaround is the same as for SCI mode but considering the low probability of
occurrence (1%), it may be preferable to keep the break generation sequence as it is.
Header time-out does not prevent wake-up from mute mode
Normally, when LINSCI is configured in LIN slave mode, if a header time-out occurs during a
LIN header reception (that is, header length > 57 bits), the LIN Header Error bit (LHE) is set,
an interrupt occurs to inform the application but the LINSCI should stay in mute mode,
waiting for the next header reception.
Problem description
The LINSCI sampling period is Tbit/16. If a LIN Header time-out occurs between the 9th and
the 15th sample of the Identifier Field Stop Bit (refer to
from mute mode. Nevertheless, LHE is set and LIN header detection flag (LHDF) is kept
cleared.
In addition, if LHE is reset by software before this 15th sample (by accessing the SCISR
register and reading the SCIDR register in the LINSCI interrupt routine), the LINSCI
generates another LINSCI interrupt (due to the RDRF flag setting).
The synch break field (14 bits).
The synch field (10 bits).
the identifier field (10 bits).
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
CPU
= 8 MHz and SCIBRR = 0xC9), the wrong break duration
Figure
165), the LINSCI wakes up