st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 138

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
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Table 57.
SPI data I/O register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register initiates the transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
Bit Name
SPIDR
5
4
3
2
1
0
MODF
7
SOD
SSM
OVR
SSI
-
SPI overrun error
Mode fault flag
Reserved, must be kept cleared
SPI output disable
SS management
SS internal mode
SPICSR register description (continued)
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see
condition (OVR) on page
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master mode (see
mode fault (MODF) on page
the SPICR register. This bit is cleared by a software sequence (an access to the
SPICSR register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode/MISO in slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead (see
page
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level
of the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
free for general-purpose I/O)
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
129).
5
133). An interrupt is generated if SPIE = 1 in the SPICR
4
133). An SPI interrupt can be generated if SPIE = 1 in
D[7:0]
R/W
Function
3
2
Slave select management on
Reset value: undefined
1
Overrun
Master
0