st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 51

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
6.5.4
6.5.5
Low power modes
Table 7.
Interrupts
The CSS or AVD interrupt events generate an interrupt if the corresponding enable control
bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM
instruction).
Table 8.
1. This interrupt allows to exit from Active Halt mode.
System integrity control/status register (SICSR, page 0)
Table 9.
CSS event detection
(safe oscillator activated as main clock)
AVD event
SICSR, page 0
Bit
Mode
7
6
Wait
Halt
PAGE
R/W
7
AVDIE
Name
PAGE
No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.
The CRSR register is frozen.
The CSS (including the safe oscillator) is disabled until Halt mode is exited. The previous
CSS configuration resumes when the MCU is woken up by an interrupt with ‘exit from Halt
mode’ capability or from the counter reset value when the MCU is woken up by a RESET.
The AVD remains active, and an AVD interrupt can be used to exit from Halt mode.
Interrupt event
Effect of low power modes on SI
SI interrupt control/wake-up capability
SICSR (page 0) register description
SICSR register page selection
Voltage detector interrupt enable
AVDIE
R/W
This bit selects the SICSR register page. It is set and cleared by software;
0: Access to SICSR register mapped in page 0
1: Access to SICSR register mapped in page 1
This bit is set and cleared by software. It enables an interrupt to be generated when
the AVDF flag changes (toggles). The pending interrupt information is automatically
cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
6
AVDF
R/W
5
LVDRF
Event flag
R/W
4
CSSD
AVDF
Description
Reserved
Function
Enable control
3
-
CSSIE
AVDIE
bit
CSSIE
R/W
2
Reset value: 000x 000x (00h)
Exit from
Supply, reset and clock
WAIT
Yes
Yes
CSSD
R/W
1
Exit from
HALT
WDGRF
No
Yes
R/W
(1)
0
51/371