st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 40

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

Central processing unit
5.3.5
Note:
40/371
Table 5.
Stack pointer register (SP)
The stack pointer is a 16-bit register which always points to the next free location in the
stack. It is decremented after data has been pushed onto the stack and incremented before
data is popped from the stack (see
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The LSB of the stack pointer (called S) can be directly accessed by an LD instruction.
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the push
and pop instructions. In the case of an interrupt, the PCL is stored at the first location
SP
Bit
R
1
0
15
7
(carry/borrow)
Name
(zero)
C
Z
CC register description (continued)
14
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Arithmetic management bit
Arithmetic management bit
This bit is driven by the SCF and RCF instructions and tested by the JRC and
This bit is set and cleared by hardware. This bit indicates that the result of the
last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero
1: The result of the last operation is zero
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an overflow
or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred
1: An overflow or underflow has occurred
JRNC instructions. It is also affected by the “bit test and branch”, shift and
rotate instructions.
13
5
Figure
SP[7:0]
R/W
R/W
12
0
4
8).
11
3
Function
10
2
Reset value: 01 FFh
9
1
R/W
R/W
8
1
0