st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 137

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Table 56.
SPI control/status register (SPICSR)
Table 57.
1:0 SPR[1:0]
SPICSR
Bit Name
Bit
7
6
4
3
2
SPIF
RO
WCOL
7
SPIF
MSTR
CPHA
Name
CPOL
Serial peripheral data transfer flag
Write collision status
SPICR register description (continued)
SPICSR register description
WCOL
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see
0: No write collision occurred
1: A write collision has been detected
Master mode
Clock polarity
Clock phase
Serial clock frequency
RO
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
This bit is set and cleared by software. This bit determines the idle state of the
serial clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge
1: The second clock transition is the first capture edge
Note: The slave must have the same CPOL and CPHA settings as the master.
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
Note: These 2 bits have no effect in slave mode.
6
and the functions of the MISO and MOSI pins are reversed.
OVR
RO
5
MODF
RO
4
Master mode fault (MODF) on page
Reserved
Function
Function
3
-
SOD
R/W
2
Reset value: 0000 0000 (00h)
Figure
On-chip peripherals
SSM
R/W
133).
1
59).
R/W
SSI
137/371
0