si4330 Silicon Laboratories, si4330 Datasheet - Page 81

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Register 0Ah. Microcontroller Output Clock
Reset value = xx000110
Name
Type
Bit
7:6
5:4
2:0
Bit
3
Reserved
mclk[2:0]
clkt[1:0]
Name
D7
enlfc
Reserved
R
Reserved.
Clock Tail.
If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to
complete its operation. Setting the clkt[1:0] register will provide the addition cycles of the
clock before it shuts off.
00:
01:
10:
11:
Enable Low Frequency Clock.
When enlfc = 1 and the chip is in Sleep mode then the 32.768 kHz clock will be provided
to the microcontroller no matter what the selection of mclk[2:0] is. For example if
mclk[2:0] = ‘000’, 30 MHz will be available through the GPIO to output to the microcon-
troller in all Idle or RX states. When the chip is commanded to Sleep mode the 30 MHz
clock will become 32.768 kHz.
Microcontroller Clock.
Different clock frequencies may be selected for configurable GPIO clock output. All clock
frequencies are created by dividing the XTAL except for the 32 kHz clock which comes
directly from the 32 kHz RC Oscillator. The mclk[2:0] setting is only valid when xton = 1
except the 111.
000:
001:
010:
011:
100:
101:
110:
111:
D6
0 cycle
128 cycles
256 cycles
30 MHz
15 MHz
10 MHz
4 MHz
3 MHz
2 MHz
1 MHz
32.768 kHz
512 cycles
D5
clkt[1:0]
R/W
Preliminary Rev 0.2
D4
Function
enlfc
R/W
D3
D2
mclk[2:0]
R/W
D1
Si4330
D0
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