si4330 Silicon Laboratories, si4330 Datasheet - Page 28

no-image

si4330

Manufacturer Part Number
si4330
Description
Si4330 Ism Receiver
Manufacturer
Silicon Laboratories
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
si4330-A0-FM
Manufacturer:
SILICON
Quantity:
740
Part Number:
si4330-A0-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
si4330-B1-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
si4330-B1-FM
Quantity:
75
Part Number:
si4330-B1-FM-02T
Manufacturer:
SILICON
Quantity:
112
Part Number:
si4330-B1-FMR
Manufacturer:
HIROSE
Quantity:
3 200
Part Number:
si4330-B1-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
si4330BDY-T1-E3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Part Number:
si4330BDY-T1-GE3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Part Number:
si4330DY-T1-E3
Manufacturer:
VISHAY
Quantity:
464
Part Number:
si4330DY-T1-E3
Manufacturer:
VISHAY
Quantity:
30 000
Company:
Part Number:
si4330DY-T1-E3
Quantity:
70 000
Si4330
The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in
“Register 1Dh. AFC Loop Gearshift Override,” on page 92), the Frequency Offset shows the results of the AFC
algorithm for the current receive slot. When selecting the preamble length, the length needs to be long enough to
settle the AFC. In general two bytes of preamble is sufficient to settle the AFC. Disabling the AFC allows the
preamble to be shortened by about 8 bits. Note that with the AFC disabled, the preamble length must still be long
enough to settle the receiver and to detect the preamble (see "6.6. Preamble Length" on page 37). The AFC
corrects the detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble is
detected, the AFC will freeze. In multi-packet mode the AFC is reset at the end of every packet and will re-acquire
the frequency offset for the next packet. An automatic reset circuit prevents excessive drift by resetting the AFC
loop when the tuning exceeds 2 times the frequency deviation (as set by fd[8:0] in register 71h and 72h) in high
band or 1 times the frequency deviation in low band. This range can be halved by the “afcbd” bit in register 1Dh.
Frequency Correction
AFC disabled
Freq Offset Register
AFC enabled
AFC
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
1D
R/W
AFC Loop Gearshift
40h
afcbd enafc afcgearh[2] afcgearh[1] afcgearh[0] afcgearl[2] afcgearl[1] afcgearl[0]
Override
28
Preliminary Rev 0.2

Related parts for si4330