si4330 Silicon Laboratories, si4330 Datasheet - Page 32

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Si4330
operation on the same frequency. The VCO integrates the resonator inductor, tuning varactor, so no external VCO
components are required.
The VCO uses capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not
be desirable so the VCO calibration may be skipped by setting the appropriate register.
5.7. Crystal Oscillator
The Si4330 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a
suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance
integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the
30 MHz crystal blank.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance
requirements and to slightly adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance
is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance". The total
internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit is a
course shift in frequency but is not binary with xlc[6:0].
The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance
requirements and to slightly adjust the frequency of the crystal oscillator. This latter function can be used to
compensate for crystal production tolerances. Utilizing the on-chip temperature sensor and suitable control
software even the temperature dependency of the crystal can be canceled.
The crystal load capacitance is programmed using register 09h. The typical value of the total on-chip (internal)
capacitance Cint can be calculated as follows:
Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift
Note that the course shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal
can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value
of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning. See more on this,
calculating Cext and crystal selection guidelines in "11. Application Notes" on page 66.
If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency Offset
field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as discussed in "3.6.
Frequency Control" on page 23.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of
the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire
system and the BOM cost is reduced. The available clock frequencies (i.e., internal division ratios) and the GPIO
configuration are discussed further in "8.2. Microcontroller Clock" on page 46.
The Si4330 may also be driven with an external 30 MHz clock signal through the XIN pin.
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
09
R/W
Crystal Oscillator Load
xtalshift
xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1]
xlc[0]
40h
Capacitance
5.8. Regulators
There are a total of six regulators integrated onto the Si4330. With the exception of the IF and Digital all regulators
are designed to operate with only internal decoupling. The IF and Digital regulators both require an external 1 µF
decoupling capacitor. All of the regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V,
and produce a nominal regulated output voltage of +1.7 V ±5%. The internal circuitry nominally operates from this
regulated +1.7 V supply.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the IF or DIG regulator
outputs.
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Preliminary Rev 0.2