si4330 Silicon Laboratories, si4330 Datasheet - Page 79

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Register 08h. Operating Mode and Function Control 2
Reset value = 00000000
Name
Type
Bit
7:5
Bit
4
3
2
1
0
antdiv[2:0]
Reserved
Reserved
Name
rxmpk
enldm
D7
ffclrrx
antdiv[2:0]
Enable Antenna Diversity.
The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
000:
001:
010:
011:
100:
101:
110:
111:
RX Multi Packet.
When the chip is selected to use FIFO Mode (dtmod[1:0]) and RX Packet Handling
(enpacrx) then it will fill up the FIFO with multiple valid packets if this bit is set, otherwise
the receiver will automatically leave the RX State after the first valid packet has been
received.
Reserved.
Enable Low Duty Cycle Mode.
If this bit is set to 1 then the chip turns on the RX regularly. The frequency should be set
in the Wake-Up Timer Period register, while the minimum ON time should be set in the
Low-Duty Cycle Mode Duration register. The FIFO mode should be enabled also.
RX FIFO Reset/Clear.
This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the
contents of the RX FIFO.
Reserved.
R/W
D6
RX state
GPIO Ant1
0
1
0
1
antenna diversity algorithm
antenna diversity algorithm
ant. div. algorithm in beacon mode
ant. div. algorithm in beacon mode
D5
Preliminary Rev 0.2
rxmpk
R/W
D4
Reserved
Function
R/W
D3
non RX state
GPIO Ant2
1
0
1
0
0
1
0
1
enldm
R/W
D2
GPIO Ant1 GPIO Ant2
0
0
1
1
0
1
0
1
ffclrrx
R/W
D1
Si4330
0
0
1
1
Reserved
R/W
D0
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