si4330 Silicon Laboratories, si4330 Datasheet - Page 6

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Si4330
L
T
I S T OF
ABLES
Table 1. DC Characteristics .......................................................................................................7
1
Table 2. Synthesizer AC Electrical Characteristics
...................................................................8
1
Table 3. Receiver AC Electrical Characteristics
.......................................................................9
1
Table 4. Auxiliary Block Specifications
...................................................................................10
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 11
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 11
Table 7. Absolute Maximum Ratings ........................................................................................ 12
Table 8. Operating Modes ........................................................................................................15
Table 9. Serial Interface Timing Parameters ............................................................................16
Table 10. Operating Modes ...................................................................................................... 18
Table 11. Frequency Band Selection ....................................................................................... 24
Table 12. RX Packet Handler Configuration ............................................................................35
Table 13. Packet Handler Registers ......................................................................................... 36
Table 14. Minimum Receiver Settling Time .............................................................................. 38
Table 15. RX Modem Configurations for FSK and GFSK ........................................................ 39
Table 16. Filter Bandwidth Parameters .................................................................................... 41
Table 17. Channel Filter Bandwidth Settings ........................................................................... 42
Table 18. ndec[2:0] Settings ..................................................................................................... 43
Table 19. RX Modem Configuration for OOK with Manchester Disabled ................................. 44
Table 20. RX Modem Configuration for OOK with Manchester Enabled ................................. 44
Table 21. POR Parameters ...................................................................................................... 45
Table 22. Temperature Sensor Range ..................................................................................... 50
Table 23. Antenna Diversity Control ......................................................................................... 57
Table 24. Receiver Bill of Materials ..........................................................................................60
Table 25. Recommended Crystal Parameters ......................................................................... 66
Table 26. RX Matching for Different Bands .............................................................................. 67
Table 27. Register Descriptions ............................................................................................... 68
Table 28. Interrupt or Status 1 Bit Set/Clear Description ......................................................... 73
Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? ............. 73
Table 30. Interrupt or Status 2 Bit Set/Clear Description ........................................................ 75
Table 31. Detailed Description of Status Registers when not Enabled as Interrupts ............... 75
Table 32. Internal Analog Signals Available on the Analog Test Bus .................................... 114
Table 33. Internal Digital Signals Available on the Digital Test Bus .......................................115
Preliminary Rev 0.2
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