si5315 Silicon Laboratories, si5315 Datasheet - Page 48

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

Si5315
48
15,19,
5, 10,
20,31
Pin #
32
11
12
13
8,
7
6
9
XTAL/CLOCK
Pin Name
AUTOSEL
CKIN2+
CKIN2–
GND
V
XB
XA
DD
GND
V
Table 18. Si5315 Pin Descriptions (Continued)
I/O
DD
I
I
I
I
Signal Level
3-Level
3-Level
Analog
Supply
Supply
Preliminary Rev. 0.2
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V
5
10
32
A 1.0 µF should also be placed as close to device as is prac-
tical.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. Crystal or reference clock
selection is set by the XTAL/CLOCK pin.
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
This pin has both a weak pull-up and a weak pull-down and
defaults to M.
L = Crystal
M = Clock (Default)
H = Reserved
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
0.1 µF
0.1 µF
0.1 µF
Description
DD
pins: