si5315 Silicon Laboratories, si5315 Datasheet - Page 20

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

Si5315
4. Frequency Plan Tables
For ease of use, the Si5315 is pin controlled to enable simple device configuration of the frequency plan and PLL
loop bandwidth via a predefined look up table. The DSPLL has been optimized for each frequency multiplication
and PLL loop bandwidth provided in Table 7 on page 21.
Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels
determined by the supply voltage: V
and Ground. If the input pin is left floating, it is driven to nominally half of
DD
V
. Effectively, this creates three logic levels for these controls. See sections 7. "Power Supply Filtering" on page
DD
44 and 1.2. "Three-Level (3L) Input Pins (With External Resistors)" on page 10 for additional information.
4.1. Frequency Multiplication Plan
The input to output clock multiplication is set by the 3-level FRQSEL[3:0] pins. The device provides a wide range of
commonly used SyncE, SONET/SDH, and PDH frequency translations. The CKIN1 and CKIN2 inputs must be the
same frequency as specified in Table 7. Both CKOUT1 and CKOUT2 outputs are at the same frequency.
4.1.1. PLL Loop Bandwidth Plan
The Si5315's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency multiplication, its corresponding
loop bandwidth is provided in a simple look up table. (See Table 7 on page 21.) The loop bandwidth (BW) is
digitally programmable using the 3-level BWSEL [1:0] and FRQTBL input pins.
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Preliminary Rev. 0.2