si5315 Silicon Laboratories, si5315 Datasheet - Page 47

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

10. Pin Descriptions: Si5315
Pin assignments are preliminary and subject to change.
Pin #
1
2
3
4
Pin Name
FRQTBL
LOS1
LOS2
RST
I/O
O
O
I
I
AUTOSEL
FRQTBL
LOS1
LOS2
Signal Level
Table 18. Si5315 Pin Descriptions
GND
VDD
RST
XA
XB
LVCMOS
LVCMOS
LVCMOS
3-Level
1
2
3
4
5
6
7
8
9
36
10 11 12 13 14 15 16 17
35
Preliminary Rev. 0.2
34
33
GND
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5315 will perform an internal self-calibration when
a valid input signal is present.
This pin has a weak pull-up.
Frequency Table Select.
Selects frequency table. (Table 7 on page 21.)
Si5315A supports L/M/H.
Si5315B supports only L/M for normal operation.
H is reserved.
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
Pad
32
31
30
29
28
18
27
26
25
24
23
22
21
20
19
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
BWSEL1
BWSEL0
CS_CA
GND
GND
Description
Si5315
47