si5315 Silicon Laboratories, si5315 Datasheet
si5315
Manufacturer Part Number
si5315
Description
Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
Manufacturer
Silicon Laboratories
Datasheet
1.SI5315.pdf
(56 pages)
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si5315-C
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AUK
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si53154-A01AGMR
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S
C
Features
Applications
Description
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous
Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock
inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-
multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency
and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1
rates. The Si5315 is based on Silicon Laboratories' 3rd-generation DSPLL
technology, which provides any-rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO and loop
filter components. The DSPLL loop bandwidth is user programmable, providing jitter
performance optimization at the application level.
Functional Block Diagram
Preliminary Rev. 0.2 12/08
Loss of Signal 1
Loss of Signal 2
Y N C H R O N O U S
L O C K
Loss of Lock
Provides jitter attenuation and frequency
translation between SONET/PDH and
Ethernet
Supports ITU-T G.8262 Synchronous
Ethernet equipment slave clocks (EEC
option 1 and 2) requirements
Two clock inputs/two clock outputs
Input frequency range: 8 kHz–644 MHz
Output frequency range: 8 kHz–644 MHz
Very low jitter: 0.6 ps (12 kHz–20 MHz)
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 to 8.4 kHz
Synchronous Ethernet Line Cards
SONET OC-3/12/48 Line Cards
GPON OLT/ONU
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Clock In 1
Clock In 2
Loop Bandwidth Select[1:0]
Frequency Table Select
Frequency Select[3:0]
M
Si5315
U L T I PL I E R
E
Status/Control
XTAL/Clock
DSPLL
T H E R N E T
®
Copyright © 2008 by Silicon Laboratories
Automatic/Manual hitless reference
switching and holdover during loss of
reference inputs clock
Programmable output clock signal
format: LVPECL, LVDS, CML or CMOS
40 MHz crystal or XO reference
Single supply: 1.8, 2.5, or 3.3 V
Loss of lock and loss of signal alarms
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to +85 ºC
Carrier Ethernet Switches Routers
DSLAM
T1/E1/DS3/E3 Line Cards
Manual/Auto Clock Selection
Clock Switch/Clock Active Indicator
XTAL/Clock
/ T
E LE C O M
Clock Out 1
Output Signal Format[1:0]
Clock Out 2
Clock 2 Disable/PLL Bypass
VDD (1.8, 2.5, or 3.3 V)
GND
J
I T T E R
P
®
R E L I M I N A R Y
AUTOSEL
FRQTBL
A
LOS1
LOS2
GND
VDD
RST
XA
XB
T T E N U A T I N G
Ordering Information:
1
2
3
4
5
6
7
8
9
Pin Assignments
36
10 11 12 13 14 15 16 17
See page 51.
35
34
Si5315
33
GND
D
Pad
32
A TA
31
30
29
28
18
S
27
26
25
24
23
22
21
20
19
H E E T
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
BWSEL1
BWSEL0
CS_CA
GND
GND
Si5315
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