si5315 Silicon Laboratories, si5315 Datasheet - Page 39

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

5.2. Output Clock Drivers
The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,
and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0]
pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for
output driver specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L
(ground), M (V
load being driven.
For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals and should be
externally shorted together to obtain the drive strength specified in Table 2, “DC Characteristics”.
Figure 15. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together)
CKOUTn
DD
/2), and H (V
Si5315
Table 15. Output Signal Format Selection (SFOUT)
DD
Figure 14. Typical Differential Output Circuit
). Table 15 shows the signal formats based on the supply voltage and the type of
SFOUT[1:0]
Z0 = 50
CKOUTn
All Others
Z0 = 50
HM
MH
LM
ML
HL
LH
Preliminary Rev. 0.2


Si5315
Outputs Together for Greater Strength
Low-swing LVDS
Optionally Tie CKOUTn
Signal Format
Reserved
Disabled
LVPECL
CMOS
LVDS
CML
CMOS
Logic
100

Rcvr
Si5315
39