si5315 Silicon Laboratories, si5315 Datasheet - Page 32

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

Si5315
4.2.4. Recommended Reset Guidelines
Follow the recommended RESET guidelines in Table 8 when reset should be applied to a device.
4.2.5. Hitless Switching with Phase Build-Out
Silicon Laboratories switching technology performs "phase build-out" to minimize the propagation of phase
transients to the clock outputs during input clock switching. All switching between input clocks occurs within the
input multiplexor and phase detector circuitry. The phase detector circuitry continually monitors the phase
difference between each input clock and the DSPLL output clock, f
clock signal at a specified phase offset relative to f
At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for
the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the
new clock's phase offset so that the phase of the output clock is not disturbed. The phase difference between the
two input clocks is absorbed in the phase detector's offset value, rather than being propagated to the clock output.
The switching technology virtually eliminates the output clock phase transients traditionally associated with clock
rearrangement (input clock switching). The Maximum Time Interval Error (MTIE) and maximum slope for clock
output phase transients during clock switching are given in (Table 3, “AC Characteristics”). These values fall
significantly below the limits specified in the ITU-T G.8262, Telcordia GR-1244-CORE, and GR-253-CORE
requirements.
4.3. Input Clock Control
This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless
switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two
clocks differ in frequency by more than 100 ppm.
4.3.1. Manual Clock Selection
Manual control of input clock selection is chosen via the CS_CA pin according to Table 9 and Table 10.
32
Pin #
22
23
24
25
26
27
11
2
Si5315 Pin Name
XTAL/CLOCK
AUTOSEL
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
BWSEL0
BWSEL1
FRQTBL
Table 9. Automatic/Manual Clock Selection
M
H
L
Table 8. Si5315 Pins and Reset
Preliminary Rev. 0.2
OSC
Automatic non-revertive
Clock Selection Mode
so that the phase offset is maintained by the PLL circuitry.
Automatic revertive
Must Reset after Changing
Manual
OSC
. The phase detector circuitry can lock to a
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes