spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 70

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
2-44
No.
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
Flags input hold time after RXC falling edge
TXC rising edge to FST out (bl) high
TXC rising edge to FST out (bl) low
TXC rising edge to FST out (wr) high
TXC rising edge to FST out (wr) low
TXC rising edge to FST out (wl) high
TXC rising edge to FST out (wl) low
TXC rising edge to data out enable from high
impedance
TXC rising edge to Transmitter #0 drive enable
assertion
TXC rising edge to data out valid
TXC rising edge to data out high impedance
TXC rising edge to Transmitter #0 drive enable
deassertion
FST input (bl, wr) setup time before TXC falling
edge
FST input (wl) to data out enable from high
impedance
FST input (wl) to Transmitter #0 drive enable
assertion
FST input (wl) setup time before TXC falling edge
FST input hold time after TXC falling edge
Flag output valid after TXC rising edge
2
3
Characteristics
4, 5, 7
8
2
2
Table 2-22.
DSP56301 Technical Data, Rev. 10
3
Symbol
ESSI Timings (Continued)
Expression
Min
21.0
21.0
6.0
0.0
2.0
2.5
4.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80 MHz
Max
29.0
15.0
31.0
17.0
31.0
17.0
33.0
19.0
30.0
16.0
31.0
17.0
31.0
17.0
34.0
20.0
20.0
10.0
31.0
16.0
34.0
20.0
27.0
31.0
32.0
18.0
—
—
—
—
—
—
—
—
Min
21.0
21.0
6.0
0.0
2.0
2.5
4.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100 MHz
Freescale Semiconductor
Max
29.0
15.0
31.0
17.0
31.0
17.0
33.0
19.0
30.0
16.0
31.0
17.0
31.0
17.0
34.0
20.0
20.0
10.0
31.0
16.0
34.0
20.0
27.0
31.0
32.0
18.0
—
—
—
—
—
—
—
—
Cond-
ition
i ck s
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
—
—
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns