spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 104

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Design Considerations
As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first
definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case
thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will
yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric,
thermal characterization parameter or Ψ
of the junction temperature in natural convection when the surface temperature of the package is used. Remember
that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of
the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a
40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4.2 Electrical Design Considerations
Use the following list of recommendations to ensure correct DSP operation.
4-2
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•
•
•
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•
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•
If the temperature of the package case (T
computed from the value obtained by the equation (T
Provide a low-impedance path from the board power supply to each
board ground to each
Use at least six 0.01–0.1 μF bypass capacitors positioned as close as possible to the four sides of the
package to connect the
Ensure that capacitor leads and associated printed circuit traces that connect to the chip
are less than 0.5 inch per capacitor lead.
Use at least a four-layer PCB with two inner layers for
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This
recommendation particularly applies to the address and data buses as well as the
TA
Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the
All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with
internal pull-up resistors (
Take special care to minimize noise levels on the
The following pins must be asserted after power-up:
, and
BG
pins. Maximum PCB trace lengths on the order of 6 inches are recommended.
GND
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (for example, either GND or V
V
V
CC
CC
TRST
pin.
power source to
and
,
JT
TMS
GND
DSP56301 Technical Data, Rev. 10
, has been defined to be (T
,
circuits.
DE
).
T
) is determined by a thermocouple, thermal resistance is
CAUTION
GND
.
V
CCP
RESET
J
,
– T
V
GND
CC
T
)/P
and
and
J
P
, and
– T
D
CC
.
GND
TRST
T
).
)/P
GND
.
V
D
CC
.
. This value gives a better estimate
P1
pin on the DSP and from the
pins.
IRQA
Freescale Semiconductor
,
IRQB
V
CC
and
,
IRQC
GND
,
IRQD
pins
,