spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 21

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
SCK0
PC3
SRD0
PC4
STD0
PC5
Signal Name
Input/Output
Input or Output
Input/Output
Input or Output
Input/Output
Input or Output
Table 1-12.
Type
Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
Input
Input
Input
State During
Reset
DSP56301 Technical Data, Rev. 10
Serial Clock
Provides the serial bit rate clock for the ESSI interface for both the transmitter
and receiver in Synchronous modes, or the transmitter only in Asynchronous
modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6 T
(that is, the system clock frequency must be at least three times the external
ESSI clock frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
Port C 3
The default configuration following reset is GPIO. For PC3, signal direction is
controlled through PRR0. The signal can be configured as an ESSI signal
SCK0 through PCR0.
This input is 5 V tolerant.
Serial Receive Data
Receives serial data and transfers the data to the ESSI receive shift register.
SRD0 is an input when data is being received.
Port C 4
The default configuration following reset is GPIO. For PC4, signal direction is
controlled through PRR0. The signal can be configured as an ESSI signal
SRD0 through PCR0.
This input is 5 V tolerant.
Serial Transmit Data
Transmits data from the serial transmit shift register. STD0 is an output when
data is being transmitted.
Port C 5
The default configuration following reset is GPIO. For PC5, signal direction is
controlled through PRR0. The signal can be configured as an ESSI signal
STD0 through PCR0.
This input is 5 V tolerant.
Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal Description
1-17