spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 61

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
346
Notes:
300
301
302
305
307
308
309
310
312
313
314
315
316
317
324
325
326
327
328
329
No.
No.
345
HDBDR High from Read Data Strobe Deassertion
HRST Assertion to Host Port Pins High Impedance
Access Cycle Time
HA[10–0], HAEN Setup to Data Strobe Assertion
HA[10–0], HAEN Valid Hold from Data Strobe Deassertion
Data Strobe Deasserted Width
HBS Asserted Pulse Width
HBS Assertion to Data Strobe Assertion
HBS Assertion to Data Strobe Deassertion
HBS Deassertion to Data Strobe Deassertion
Data Out Active from Read Data Strobe Assertion
Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted—HTA Asserted)
Data Out Valid Hold from Read Data Strobe Deassertion
Data Out High Impedance from Read Data Strobe Deassertion
Data In Valid Setup to Write Data Strobe Deassertion
Data In Valid Hold from Write Data Strobe Deassertion
HTA Assertion to Data Strobe Deassertion
HTA High Impedance from Data Strobe Deassertion
HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)
HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)
HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)
1.
2.
3.
4.
5.
6.
7.
8.
The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.
The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.
HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.
“LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
LT ≥ 1.
Values are valid for V
1
Table 2-19.
Table 2-18.
1
Characteristic
Characteristic
CC
1
= 3.3 ± 0.3V
Universal Bus Mode, Synchronous Port A Type Host Timing
Universal Bus Mode Timing Parameters (Continued)
1
3
1
1,2
DSP56301 Technical Data, Rev. 10
1
1
3
3
2
1,2
4
4
3
1
1
3
100 MHz: 2.5 × T
100 MHz: 2.5 × T
100 MHz: 1.5 × T
80 MHz: 2.5 × T
80 MHz: 2.5 × T
80 MHz: 1.5 × T
(LT + 1) × T
100 MHz: T
80 MHz: T
Expression
Expression
1.5 × T
3 × T
C
C
C
C
C
− 4.9
− 6.0
C
− 4.0
C
C
C
C
C
+ 24.7
+ 2.9
+ 3.3
+ 21.5
+ 2.3
+ 2.6
7
Min
Min
37.5
34.1
22.1
18.8
5.8
0.0
4.1
2.5
1.7
1.7
8.3
0.0
0.0
6.5
0.0
—
—
—
—
—
—
—
80 MHz
80 MHz
AC Electrical Characteristics
Max
Max
22.2
22.2
18.9
12.0
15.3
55.9
7.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
Min
30.0
27.3
17.6
15.0
4.6
0.0
3.3
2.0
1.3
1.3
6.6
0.0
0.0
4.0
0.0
—
—
—
—
—
—
—
100 MHz
100 MHz
Max
Max
19.6
19.6
16.9
12.2
46.5
6.0
9.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Unit
2-35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns