spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 66

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
2-40
Notes:
No.
349
350
351
352
353
354
355
356
357
358
359
360
361
HCLK to Signal Valid Delay—Bussed Signals
HCLK to Signal Valid Delay—Point to Point
Float to Active Delay
Active to Float Delay
Input Set Up Time to HCLK—Bussed Signals
Input Set Up Time to HCLK—Point to Point
Input Hold Time from HCLK
Reset Active Time After Power Stable
Reset Active Time After HCLK Stable
Reset Active to Output Float Delay
HCLK Cycle Time
HCLK High Time
HCLK Low Time
1.
2.
3.
For standard PCI timing, see the PCI Local Bus Specification, Rev. 2.0, especially Chapters 3 and 4.
The HI32 supports these timings for a PCI bus operating at 33 MHz for a DSP clock frequency of 56 MHz and above. The DSP
core operating frequency should be greater than 5/3 of the PCI bus frequency to maintain proper PCI operation.
HGNT has a setup time of 10 ns. HREQ has a setup time of 12 ns.
Impedance
OUTPUT
OUTPUT
DELAY
INPUT
HCLK
High
Characteristic
Table 2-20.
351
10
349
350
360
DSP56301 Technical Data, Rev. 10
Figure 2-36.
352
PCI Mode Timing Parameters
359
Symbol
t
t
t
RST-CLK
RST-OFF
t
VAL(ptp)
SU(ptp)
t
t
t
t
t
t
HIGH
t
CYC
LOW
OFF
t
RST
VAL
ON
SU
t
PCI Timing
H
361
353
354
10.0, 12.0
100.0
Min
30.0
11.0
11.0
2.0
2.0
2.0
7.0
0.0
1.0
—
—
80 MHz
355
1
Max
11.0
12.0
28.0
40.0
—
—
—
—
—
—
—
—
—
10.0, 12.0
100.0
Min
30.0
11.0
11.0
2.0
2.0
2.0
7.0
0.0
1.0
Freescale Semiconductor
—
—
100 MHz
Max
11.0
12.0
28.0
40.0
—
—
—
—
—
—
—
—
—
Unit
ms
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns