spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 69

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spakdsp301vl100

Manufacturer Part Number
spakdsp301vl100
Description
Dsp56301 24-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
2.5.8
Freescale Semiconductor
No.
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
Clock cycle
Clock high period
For internal clock
For external clock
Clock low period
For internal clock
For external clock
RXC rising edge to FSR out (bl) high
RXC rising edge to FSR out (bl) low
RXC rising edge to FSR out (wr) high
RXC rising edge to FSR out (wr) low
RXC rising edge to FSR out (wl) high
RXC rising edge to FSR out (wl) low
Data in setup time before RXC (SCK in
Synchronous mode) falling edge
Data in hold time after RXC falling edge
FSR input (bl, wr) high before RXC falling edge
FSR input (wl) high before RXC falling edge
FSR input hold time after RXC falling edge
Flags input setup before RXC falling edge
ESSI0/ESSI1 Timing
1
Characteristics
1X SCLK
(Output)
TXD
4, 5, 7
Figure 2-39.
2
2
DSP56301 Technical Data, Rev. 10
Table 2-22.
2
Symbol
SCI Asynchronous Mode Timing
t
SSICC
412
414
ESSI Timings
Expression
Data Valid
2 × T
2 × T
1.5 × T
1.5 × T
3 × T
4 × T
411
C
C
− 10.0
− 10.0
C
C
C
C
413
415
Min
50.0
37.5
15.0
18.8
15.0
18.8
10.0
19.0
23.0
23.0
19.0
5.0
3.0
1.0
3.5
3.0
0.0
5.5
80 MHz
Max
37.0
22.0
37.0
22.0
39.0
24.0
39.0
24.0
36.0
21.0
37.0
22.0
AC Electrical Characteristics
Min
30.0
40.0
10.0
15.0
10.0
15.0
10.0
19.0
23.0
23.0
19.0
5.0
3.0
1.0
3.5
3.0
0.0
5.5
100 MHz
Max
37.0
22.0
37.0
22.0
39.0
24.0
39.0
24.0
36.0
21.0
37.0
22.0
Cond-
ition
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck s
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
6
Unit
2-43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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