spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 67

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.5.7
Freescale Semiconductor
415
No.
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
Synchronous clock cycle
Clock low period
Clock high period
Output data setup to clock falling edge (internal
clock)
Output data hold after clock rising edge (internal
clock)
Input data setup time before clock rising edge
(internal clock)
Input data not valid before clock rising edge
(internal clock)
Clock falling edge to output data valid (external
clock)
Output data hold after clock rising edge (external
clock)
Input data setup time before clock rising edge
(external clock)
Input data hold time after clock rising edge (external
clock)
Asynchronous clock cycle
Clock low period
Clock high period
Output data setup to clock rising edge (internal
clock)
Output data hold after clock rising edge (internal
clock)
SCI Timing
PCI Signals
POWER
HRST
HCLK
Characteristics
1
Figure 2-37.
DSP56301 Technical Data, Rev. 10
Table 2-21.
Symbol
t
t
SCC
ACC
2
3
356
PCI Reset Timing
t
SCI Timing
ACC
t
t
SCC
t
SCC
SCC
/2 − 30.0
t
SCC
/4 + 0.5 × T
/4 + 0.5 × T
Expression
/4 + 0.5 × T
t
t
t
t
t
SCC
SCC
ACC
ACC
ACC
/4 − 0.5 × T
T
357
64 × T
8 × T
C
/2 − 10.0
/2 − 10.0
/2 − 10.0
/2 − 10.0
/2 − 30.0
+ 8.0
C
C
C
C
C
+ 25.0
−17.0
− 5.5
C
370.0
100.0
800.0
390.0
390.0
370.0
Min
40.0
40.0
14.3
18.8
56.3
20.5
0.0
9.0
—
—
80 MHz
358
AC Electrical Characteristics
—
Max
25.8
32.0
—
—
—
—
—
—
—
—
—
—
—
—
—
290.0
640.0
310.0
310.0
290.0
Min
80.0
30.0
30.0
15.0
50.0
18.0
8.0
0.0
9.0
100 MHz
—
—
—
Max
19.5
32.0
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
Unit
2-41
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns