IDT72T20118L6-7BB IDT, Integrated Device Technology Inc, IDT72T20118L6-7BB Datasheet - Page 45

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IDT72T20118L6-7BB

Manufacturer Part Number
IDT72T20118L6-7BB
Description
IC FIFO 65536X20 6-7NS 208BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Tr
Datasheet

Specifications of IDT72T20118L6-7BB

Function
Synchronous
Memory Size
1.3M (65K x 20)
Access Time
3.8ns
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-BGA
Configuration
Dual
Density
2.5Mb
Access Time (max)
3.8ns
Word Size
10/20Bit
Organization
128Kx20/256Kx10
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
150MHz
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
Not Compliant
Other names
72T20118L6-7BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72T20118L6-7BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. In SDR mode, X = 16 for the IDT72T2098, X = 17 for the IDT72T20108, X = 18 for the IDT72T20118, X = 19 for the IDT72T20128 for X10 mode. X = 15 for the IDT72T2098,
2. In DDR mode, X = 15 for the IDT72T2098, X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT72T20128 for X10 to X10 mode. X = 14 for the IDT72T2098,
NOTE:
1. In SDR mode, X = 15 for the IDT72T2098, X = 17 for the IDT72T20108, X = 18 for the IDT72T20118, X = 19 for the IDT72T20128 for X10 mode. X = 15 for the IDT72T2098,
2. In DDR mode, X = 15 for the IDT72T2098, X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT20128, for X10 to X10 mode. X = 14 for the IDT72T72098,
3. Offset register values are always read starting from the first location in the offset register upon initiating SREN.
SCLK
SCLK
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
SREN
X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT72T20128 for all other modes.
X = 15 for the IDT72T20108, X = 16 for the IDT72T20118, X = 17 for the IDT 72T20128 for all other modes.
X = 16 for the IDT72T20108, X = 17 for the IDT20118, X = 18 for the IDT72T20128 for all other modes.
X = 15 for the IDT72T20108, X = 16 for the IDT72T20118, X = 17 for the IDT72T20128 for all other modes.
SEN
SO
SI
t
t
SCKH
SCKH
t
t
SCLK
SCLK
t
t
t
t
Figure 26. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 25. Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
SCKL
SENS
SCKL
SENS
t
SDS
BIT 1
t
SOA
t
t
SENH
SENH
EMPTY OFFSET
BIT 0
EMPTY OFFSET
BIT X
(1)
45
BIT 1
BIT X
(1)
FULL OFFSET
BIT 0
COMMERCIAL AND INDUSTRIAL
FULL OFFSET
TEMPERATURE RANGES
BIT X
FEBRUARY 13, 2009
t
t
t
(1)
t
ENH
ENH
SDH
SOA
5996 drw28
5996 drw29
BIT X
(1)

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