IDT72T20118L6-7BB IDT, Integrated Device Technology Inc, IDT72T20118L6-7BB Datasheet - Page 13

• Manufacturer Part Number: IDT72T20118L6-7BB
• Description: IC FIFO 65536X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20118L6-7BB

• Function: Synchronous
• Memory Size: 1.3M (65K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Configuration: Dual
• Density: 2.5Mb
• Access Time (max): 3.8ns
• Word Size: 10/20Bit
• Organization: 128Kx20/256Kx10
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 150MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72T20118L6-7BB

FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determined during
Master Reset, by the state of the FWFT input.
be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
on which timing mode is in effect.
IDT STANDARD MODE
outlined in Table 4. To write data into to the FIFO, Write Enable (WEN) must
be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are listed in Table 2. This parameter
is also user programmable. See section on Programmable Flag Offset Loading.
Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go
LOW after (D-m) writes to the FIFO. If x20 Input or x20 Output bus Width is
selected, (D-m) = (32,768-m) writes for the IDT72T2098, (65,536-m) writes
for the IDT72T20108, (131,072-m) writes for the IDT72T20118 and
(262,144-m) writes for the IDT72T20128. If both x10 Input and x10 Output bus
Widths are selected, (D-m) = (65,536-m) writes for the IDT72T2098, (131,072-m)
writes for the IDT72T20108, (262,144-m) writes for the IDT72T20118 and
(524,288-m) writes for the IDT72T20128. The offset “m” is the full offset value.
The default setting for these values are listed in Table 3. This parameter is also
user programmable. See the section on Programmable Flag Offset Loading.
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x20 Input or x20 Output bus Width is selected, D = 32,768
writes for the IDT72T2098, 65,536 writes for the IDT72T20108, 131,072 writes
for the IDT72T20118 and 262,144 writes for the IDT72T20128. If both x10
Input and x10 Output bus Widths are selected, D = 65,536 writes for the
IDT72T2098, 131,072 writes for the IDT72T20108, 262,144 writes for the
IDT72T20118 and 524,288 writes for the IDT72T20128, respectively.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
The IDT72T2098/72T20108/72T20118/72T20128 support two different
Various signals, both input and output signals operate differently depending
In this mode, the status flags, FF, PAF, PAE, and EF operate in the manner
Continuing to write data into the FIFO will cause the Programmable Almost-
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
n)
. It also uses Input Ready (IR) to indicate
n
after three RCLK rising
13
Subsequent read operations will cause PAF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
register-buffered outputs. IDT Standard mode is available when the device is
configured in both Single Data Rate mode and Double Data Rate mode.
10, 11, 12, 13, 14, 15, 16, 17, 18 and 23.
FIRST WORD FALL THROUGH MODE (FWFT)
outlined in Table 5. To write data into the FIFO, WEN must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
to the FIFO. If x20 Input or x20 Output bus Width is selected, (D-m) = (32,769-m)
writes for the IDT72T2098, (65,537-m) writes for the IDT72T20108, (131,073-m)
writes for the IDT72T20118 and (262,145-m) writes for the IDT72T20128. If
both x10 Input and x10 Output bus Widths are selected, (D-m) = (65,537-m)
writes for the IDT72T2098, (131,073-m) writes for the IDT72T20108,
(262,145-m) writes for the IDT72T20118 and (524,289-m) writes for the
IDT72T20128. The offset m is the full offset value. The default setting for these
values are stated in the footnote of Table 3.
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 32,769
writes for the IDT72T2098, 65,537 writes for the IDT72T20108, 131,073 writes
for the IDT72T20118 and 262,145 writes for the IDT72T20128. If both x10 Input
and x10 Output bus Widths are selected, D = 65,537 writes for the IDT72T2098,
131,073 writes for the IDT72T20108, 262,145 writes for the IDT72T20118 and
524,289 writes for the IDT72T20128, respectively. Note that the additional word
in FWFT mode is due to the capacity of the memory plus output register.
Subsequent read operations will cause the PAF to go HIGH at the conditions
described in Table 5. If further read operations occur, without write operations,
the PAE will go LOW when there are n+1 words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, OR will go HIGH inhibiting
further read operations. REN is ignored when the FIFO is empty.
buffered, and the IR flag output is double register-buffered. FWFT mode is only
available when the device is configured in Single Data Rate mode.
21, 22, and 24.
If the FIFO is full, the first read operation will cause FF to go HIGH.
When configured in IDT Standard mode, the EF and FF outputs are double
Relevant timing diagrams for IDT Standard mode can be found in Figure
In this mode, the status flags, IR, PAF, PAE, and OR operate in the manner
Again, if no reads are performed, the PAF will go LOW after (D-m) writes
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
When configured in FWFT mode, the OR flag output is triple register-
Relevant timing diagrams for FWFT mode can be found in Figure 19, 20,
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009