IDT72T20118L6-7BB IDT, Integrated Device Technology Inc, IDT72T20118L6-7BB Datasheet - Page 4

• Manufacturer Part Number: IDT72T20118L6-7BB
• Description: IC FIFO 65536X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20118L6-7BB

• Function: Synchronous
• Memory Size: 1.3M (65K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Configuration: Dual
• Density: 2.5Mb
• Access Time (max): 3.8ns
• Word Size: 10/20Bit
• Organization: 128Kx20/256Kx10
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 150MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72T20118L6-7BB

DESCRIPTION (CONTINUED)
(SI) pin at the rising edge of SCLK. To read out the offset registers serially, set
SREN active and data can be read out via the Serial Output (SO) pin at the rising
edge of SCLK. Four default offset settings are also provided, so that PAE can
be marked at a predefined number of locations from the empty boundary and
the PAF threshold can also be marked at similar predefined values from the full
boundary. The default offset values are set during Master Reset by the state
of the FSEL0 and FSEL1 pins.
pointers are set to the first location of the internal FIFO memory, the FWFT pin
selects IDT Standard mode or FWFT mode, the bus width configuration of the
read and write port is determined by the state of IW and OW, and the default offset
values for the programmable flags are set.
location of the memory. However, the timing mode and the values stored in the
programmable offset registers before Partial Reset remain unchanged. The
flags are updated according to the timing mode and offsets in effect. PRS is useful
for resetting a device in mid-operation, when reprogramming programmable
flags would be undesirable.
respectively. The PAE flag is asserted upon the rising edge of RCLK only and
not WCLK. Similarly the PAF is asserted and updated on the rising edge of
WCLK only and not RCLK.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
During Master Reset (MRS), the following events occur: the read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
The timing of the PAE and PAF flags are synchronous to RCLK and WCLK,
4
inputs, MARK and RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at the point will be marked. Any
subsequent retransmit operation (when RT goes LOW), will reset the read
pointer to this “marked” location.
previously stated. These rates are: x20 to x20, x20 to x10, x10 to x20 and x10
to x10.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both
input and output ports will operate in either HSTL or LVTTL mode, but cannot
be selected independent of one another.
IDT’s high-speed submicron CMOS technology.
The device can be configured with different input and output bus widths as
If, at any time, the FIFO is not actively performing an operation, the chip will
A JTAG test port is provided, here the FIFO has fully functional boundary
The Double Data Rate FIFO has the capability of operating in either LVTTL
The IDT72T2098/72T20108/72T20118/72T20128 are fabricated using
This device includes a Retransmit from Mark feature that utilizes two control
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009