IDT72T20118L6-7BB IDT, Integrated Device Technology Inc, IDT72T20118L6-7BB Datasheet - Page 25

• Manufacturer Part Number: IDT72T20118L6-7BB
• Description: IC FIFO 65536X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20118L6-7BB

• Function: Synchronous
• Memory Size: 1.3M (65K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Configuration: Dual
• Density: 2.5Mb
• Access Time (max): 3.8ns
• Word Size: 10/20Bit
• Organization: 128Kx20/256Kx10
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 150MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72T20118L6-7BB

JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72T2098/72T20108/
72T20118/72T20128 incorporates the necessary tap controller and modified
pad cells to implement the JTAG facility.
program files for these devices.
TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
The Tap interface is a general-purpose port that provides access to the
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
UpdateDR
Figure 6. Boundary Scan Architecture
Instruction Register
Control Signals
25
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
The Standard JTAG interface consists of four basic elements:
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The Tap controller is a synchronous finite state machine that responds to
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Instruction Decode
Mux
5996 drw09
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009