IDT72T20118L6-7BB IDT, Integrated Device Technology Inc, IDT72T20118L6-7BB Datasheet - Page 20

• Manufacturer Part Number: IDT72T20118L6-7BB
• Description: IC FIFO 65536X20 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20118L6-7BB

• Function: Synchronous
• Memory Size: 1.3M (65K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Configuration: Dual
• Density: 2.5Mb
• Access Time (max): 3.8ns
• Word Size: 10/20Bit
• Organization: 128Kx20/256Kx10
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 150MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72T20118L6-7BB

PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. If x20 Input or x20 Output bus width is selected, PAF will go LOW
after (32,768-m) writes for the IDT72T2098, (65,536-m) writes for the
IDT72T20108, (131,072-m) writes for the IDT72T20118 and (262,144-m)
writes for the IDT72T20128. If both x10 Input and x10 Output bus widths are
selected, PAF will go LOW after (65,536-m) writes for the IDT72T2098,
(131,072-m) writes for the IDT72T20108, (262,144-m) writes for the
IDT72T20118 and (524,288-m) writes for the IDT72T20128, respectively.
The offset “m” is the full offset value. The default setting for this value is listed in
Table 3.
LOW after (32,769-m) writes for the IDT72T2098, (65,537-m) writes for the
IDT72T20108, (131,073-m) writes for the IDT72T20118 and (262,145-m)
writes for the IDT72T20128. If both x10 Input and x10 Output bus widths are
selected, PAF will go LOW after (65,537-m) writes for the IDT72T2098,
(131,073-m) writes for the IDT72T20108, (262,145-m) writes for the
IDT72T20118 and (524,289-m) writes for the IDT72T20128, respectively.
The offset m is the full offset value. The default setting for this value is listed in
Table 3.
FWFT Mode), for the relevant timing information.
write pointer to the “marked” location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 3.
the FIFO. The default setting for this value is stated in Table 3.
Q
NOTES:
1. REN is LOW.
2. t
3. Qslowest is the data output with the slowest access time, t
4. Time, t
5. REN = RCS = OE = 0.
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
SLOWEST
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
In FWFT mode, if x20 Input or x20 Output bus width is selected, PAF will go
See Figure 29, Programmable Almost-Full Flag Timing (IDT Standard and
Note, when the device is in Retransmit mode, this flag is a comparison of the
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less in
ERCLK
ERCLK
RCLK
Figure 4. Echo Read Clock and Data Output Relationship
(3)
> t
D
is greater than zero, guaranteed by design.
A
, guaranteed by design.
t
A
t
ERCLK
t
D
t
A
t
ERCLK
t
D
A
.
5996 drw07
20
and FWFT Mode), for the relevant timing information.
ECHO READ CLOCK (ERCLK)
selectable via HSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of REN and RCS.
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times.
These variations in access time maybe caused by ambient temperature, sup-
ply voltage, or device characteristics. The ERCLK output also compensates
for any trace length delays between the Qn data outputs and receiving de-
vices inputs.
effect on the ERCLK output produced by the FIFO device, therefore the
ERCLK output level transitions should always be at the same position in time
relative to the data outputs. Note, that ERCLK is guaranteed by design to be
slower than the slowest Qn, data output. Refer to Figure 4, Echo Read Clock
and Data Output Relationship, Figure 27, Echo Read Clock & Read Enable
Operation in Double Data Rate Mode and Figure 28, Echo RCLK & Echo
REN Operation for timing information.
ECHO READ ENABLE (EREN)
selectable via HSTL.
output and provides the reading device with a more effective scheme for
reading data from the Qn output port at high speeds. The EREN output is
controlled by internal logic that behaves as follows: The EREN output is active
LOW for the RCLK cycle that a new word is read out of the FIFO. That is, a
rising edge of RCLK will cause EREN to go active, LOW if both REN and RCS
are active, LOW and the FIFO is NOT empty.
See Figure 30, Programmable Almost-Empty Flag Timing (IDT Standard
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
The ERCLK output follows the RCLK input with an associated delay. This
Any variations effecting the data access time will also have a corresponding
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
The EREN output is provided to be used in conjunction with the ERCLK
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009