IDT72T20118L6-7BB IDT, Integrated Device Technology Inc, IDT72T20118L6-7BB Datasheet

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IDT72T20118L6-7BB

Manufacturer Part Number
IDT72T20118L6-7BB
Description
IC FIFO 65536X20 6-7NS 208BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Tr
Datasheet

Specifications of IDT72T20118L6-7BB

Function
Synchronous
Memory Size
1.3M (65K x 20)
Access Time
3.8ns
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-BGA
Configuration
Dual
Density
2.5Mb
Access Time (max)
3.8ns
Word Size
10/20Bit
Organization
128Kx20/256Kx10
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
150MHz
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
Not Compliant
Other names
72T20118L6-7BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72T20118L6-7BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAM
FEATURES
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Choose among the following memory organizations:
Up to 250MHz operating frequency or 5Gbps throughput in SDR mode
Up to 110MHz operating frequency or 5Gbps throughput in DDR mode
Users selectable input port to output port data rates, 500Mb/s
Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
User selectable HSTL or LVTTL I/Os
Read Enable & Read Clock Echo outputs aid high speed operation
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write Operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag
IDT72T2098
IDT72T20108 ⎯ ⎯ ⎯ ⎯ ⎯
IDT72T20118 ⎯ ⎯ ⎯ ⎯ ⎯
IDT72T20128 ⎯ ⎯ ⎯ ⎯ ⎯
TRST
HSTL
MRS
PRS
TMS
TDO
TCK
Vref
OW
TDI
IW
⎯ ⎯ ⎯ ⎯ ⎯
32,768 x 20/65,536 x 10
65,536 x 20/131,072 x 10
131,072 x 20/262,144 x 10
262,144 x 20/524,288 x 10
(BOUNDARY SCAN)
WCS
CONFIGURATION
WRITE CONTROL
WRITE POINTER
JTAG CONTROL
CONTROL
WEN
RESET
HSTL I/0
LOGIC
LOGIC
BUS
2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10
131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10
WSDR
WCLK
OE
131,072 x 20 or 262,144 x 10
262,144 x 20 or 524,288 x 10
65,536 x 20 or 131,072 x 10
OUTPUT REGISTER
32,768 x 20 or 65,536 x 10
INPUT REGISTER
D
Q
0
0
-D
RAM ARRAY
-Q
n
n
(x20, x10)
(x20, x10)
1
• • • • •
can default to one of four preselected offsets
Dedicated serial clock input for serial programming of flag offsets
User selectable input and output port bus sizing
-x20 in to x20 out
-x20 in to x10 out
-x10 in to x20 out
-x10 in to x10 out
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
Output enable puts data outputs into High-Impedance state
JTAG port, provided for Boundary Scan function
208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (-40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
OFFSET REGISTER
READ POINTER
EREN
LOGIC
ERCLK
CONTROL
FLAG
LOGIC
READ
SREN
SEN
IDT72T20118, IDT72T20128
IDT72T2098, IDT72T20108
RCLK
REN
RCS
SCLK
FEBRUARY 2009
5996 drw01
MARK
RSDR
RT
PAF
PAE
FSEL0
FSEL1
FF/IR
EF/OR
FWFT
SI
SO
DSC-5996/11

Related parts for IDT72T20118L6-7BB

IDT72T20118L6-7BB Summary of contents

Page 1

VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION 32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10 131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10 FEATURES • • • • • Choose among the following memory organizations: ...

Page 2

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PIN CONFIGURATIONS A1 BALL PAD CORNER DNC D1 CC ...

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IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 DESCRIPTION: The IDT72T2098/72T20108/72T20118/72T20128 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) ...

Page 4

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 DESCRIPTION (CONTINUED) (SI) pin at the rising edge of SCLK. To read ...

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IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PARTIAL RESET (PRS) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) WRITE CHIP SELECT ...

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IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PIN DESCRIPTION Symbol & Name I/O TYPE Pin No Data ...

Page 7

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PIN DESCRIPTION (CONTINUED) Symbol & Name I/O TYPE Pin No. RCS HSTL-LVTTL ...

Page 8

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PIN DESCRIPTION (CONTINUED) Symbol & Name I/O TYPE Pin No. WSDR (1) ...

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IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to ...

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... Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. (1) = 2.5V ± 5 -40°C to +85° Commercial Commercial IDT72T2098L4 IDT72T2098L5 IDT72T20108L4 IDT72T20108L5 IDT72T20108L6-7 IDT72T20108L10 IDT72T20118L4 IDT72T20118L5 IDT72T20118L6-7 IDT72T20118L10 IDT72T20128L4 IDT72T20128L5 IDT72T20128L6-7 IDT72T20128L10 Min. Max. Min. Max. — 250 — 200 — 110 — 100 ...

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IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input ...

Page 12

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 OUTPUT ENABLE & DISABLE TIMING Output Enable & Output ...

Page 13

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) ...

Page 14

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 TABLE 3 — DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72T2098, 72T20108, 72T20118, 72T20128 FSEL1 ...

Page 15

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 WSDR RSDR WEN REN SEN ...

Page 16

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 RETRANSMIT FROM MARK OPERATION The Retransmit from Mark feature allows FIFO data ...

Page 17

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 – Dn) Data inputs for 20-bit ...

Page 18

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PAF flags will not be updated. The write and read clocks can ...

Page 19

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 OUTPUT ENABLE (OE) When Output Enable is LOW, the parallel output buffers ...

Page 20

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW ...

Page 21

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 TABLE 7 — BUS-MATCHING WRITE TO READ RATIO x20 DDR Input to ...

Page 22

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED) x20 DDR Input ...

Page 23

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 TABLE 8 — T MEASUREMENT SKEW Data Port Status Flags Configuration EF ...

Page 24

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 JTAG TIMING SPECIFICATION t 1 TCK t 3 TDI/ TMS TDO t ...

Page 25

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are ...

Page 26

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K Input = TMS NOTES: 1. Five consecutive TCK cycles with ...

Page 27

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted ...

Page 28

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 MRS t RSS REN t RSS WEN t RSS (2) FWFT t ...

Page 29

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 PRS t RSS REN t RSS WEN t RSS RT t RSS ...

Page 30

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K WRITE WCLK 1 (1) t SKEW1 ...

Page 31

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 31 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 32

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 RCLK t t ENS ENH REN NO OPERATION t REF EF t ...

Page 33

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 33 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 34

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 34 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 35

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 35 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 36

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 36 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 37

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 37 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 38

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 RCLK t ENS REN t ENS t ENH RCS ...

Page 39

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 39 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 40

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 40 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 41

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 41 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 42

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 42 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 43

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 43 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 44

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 44 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 45

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K SCLK t t SCKH SCKL SCLK t t SENS SEN t ...

Page 46

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL 46 TEMPERATURE RANGES FEBRUARY 13, 2009 ...

Page 47

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 WCLK t ENS WEN ...

Page 48

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K CLKL1 CLKL1 WCLK t t ENS ENH WEN PAF D ...

Page 49

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by ...

Page 50

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 FWFT FWFT WRITE CLOCK WCLK IDT WRITE ENABLE WEN 72T2098 72T20108 INPUT ...

Page 51

ORDERING INFORMATION XXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts ...

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