LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 576

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Univeral Serial Bus (USB) Controller
USBCSRL0 Device Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
576
Bit/Field
Bit/Field
SETENDC
W1C
1
0
7
6
5
4
3
7
0
RXRDYC
W1C
6
0
STALL
W1C
SETENDC
DATAEND
RXRDYC
SETEND
5
0
RXRDY
TXRDY
STALL
Name
Name
SETEND
RO
4
0
DATAEND
W1C
3
0
R/W1S
R/W0C
W1C
W1C
W1C
W1C
Type
Type
RO
STALLED
R/W0C
2
0
TXRDY
R/W1S
Reset
Reset
1
0
0
0
0
0
0
0
0
RXRDY
Preliminary
RO
0
0
Description
Transmit Packet Ready
The CPU sets this bit after loading a data packet into the FIFO. It is
cleared automatically when a data packet has been transmitted. An
interrupt is also generated at this point.
Receive Packet Ready
This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The CPU should clear this bit, by writing
a 0 when the packet has been read from the FIFO. This acknowledges
that data has been read from the FIFO.
Description
Setup End Clear
The CPU writes a 1 to this bit to clear the SETEND bit.
RXRDY Clear
The CPU writes a 1 to this bit to clear the RXRDY bit.
Send Stall
The CPU writes a 1 to this bit to terminate the current transaction. The
STALL handshake is transmitted, and then this bit is cleared
automatically.
Setup End
This bit is set when a control transaction ends before the DataEnd bit
has been set. An interrupt is generated and the FIFO flushed at this
time. The bit is cleared by the CPU writing a 1 to the SETENDC bit.
Data End
The CPU sets this bit:
■
■
■
It is cleared automatically.
When setting TXRDY for the last data packet
When clearing RXRDY after unloading the last data packet
When setting TXRDY for a zero-length data packet
June 02, 2008