LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 122

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
System Control
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
122
Bit/Field
31:25
23:17
15:7
5:4
2:0
24
16
RO
RO
6
3
31
15
0
0
RO
RO
Register 32: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
30
14
0
0
RO
RO
29
13
reserved
reserved
reserved
reserved
reserved
0
0
Name
CAN0
WDT
ADC
HIB
reserved
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0
9
0
0
0
0
0
0
0
0
0
0
Preliminary
CAN0
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Reset Control. Reset control for CAN unit 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC0 Reset Control. Reset control for SAR ADC module 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
HIB Reset Control. Reset control for the Hibernation module.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Reset Control. Reset control for Watchdog unit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
23
0
7
0
R/W
HIB
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
reserved
RO
RO
20
0
4
0
WDT
R/W
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
June 02, 2008
ADC
R/W
RO
16
0
0
0