LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 554
LM3S5632
Manufacturer Part Number
LM3S5632
Description
Lm3s5632 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5632.pdf
(685 pages)
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Reset
Reset
Type
Type
Univeral Serial Bus (USB) Controller
USBIE Host Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
USBIE Device Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
554
Host
Device
Bit/Field
7:6
RO
5
4
3
2
1
0
RO
7
0
7
0
reserved
reserved
RO
RO
Register 8: USB Interrupt Enable (USBIE), offset 0x00B
USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. By
default, interrupt 1 and 2 are enabled.
6
0
6
0
DISCON
DISCON
R/W
R/W
RESUME
SUSPND
reserved
DISCON
5
0
5
0
RESET
CONN
Name
SOF
CONN
CONN
R/W
R/W
4
0
4
0
SOF
R/W
SOF
R/W
3
0
3
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
BABBLE
RESET
R/W
R/W
2
1
2
1
RESUME
RESUME
R/W
R/W
Reset
1
1
1
1
0
0
0
0
1
1
0
SUSPND
SUSPND
Preliminary
R/W
R/W
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Disconnect Interrupt
Set by CPU to enable DISCON in USBIS.
Enable Connect Interrupt
Set by CPU to enable CONN in USBIS.
Enable Start-of-Frame Interrupt
Set by CPU to enable SOF in USBIS.
Enable Reset Interrupt
Set by CPU to enable RESET in USBIS.
Enable Resume Interrupt
Set by CPU to enable RESUME in USBIS.
Enable Suspend Interrupt
Set by CPU to enable SUSPEND in USBIS.
June 02, 2008
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