LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 270

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
General-Purpose Input/Outputs (GPIOs)
GPIO Analog Mode Select (GPIOAMSEL)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
Offset 0x528
Type R/W, reset 0x0000.0000
270
Bit/Field
31:4
3:0
RO
RO
31
15
0
0
RO
RO
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528
Note:
The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because
the GPIOs may be driven by a 5V source and affect analog operation, analog circuitry requires
isolation from the pins when not used in their analog function.
Each bit of this register controls the isolation circuitry for circuits that share the same pin as the
GPIO bit lane.
Note:
30
14
0
0
GPIOAMSEL
RO
RO
29
13
reserved
0
0
Name
If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be written
to 1 to disable the analog isolation circuit.
This register is only valid for ports D and E.
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
reserved
RO
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Analog Mode Select
Note:
The reset state of this register is 0 for all bit lanes.
Value
0
1
RO
RO
23
0
7
0
Description
Analog function of the pin is disabled, the isolation is enabled,
and the pin is capable of digital functions as specified by the
other GPIO configuration registers.
Analog function of the pin is enabled, the isolation is disabled,
and the pin is capable of analog functions.
This register and bits are required only for GPIO bit lanes that
share analog function through a unified I/O pad.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
GPIOAMSEL
0
2
0
R/W
RO
17
0
1
0
June 02, 2008
R/W
RO
16
0
0
0