LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 154
LM3S5632
Manufacturer Part Number
LM3S5632
Description
Lm3s5632 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5632.pdf
(685 pages)
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Reset
Reset
Type
Type
Internal Memory
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset -
8.6
154
Bit/Field
31:1
RO
RO
0
31
15
0
0
RO
RO
Register 1: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROM controller state.
30
14
Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
0
0
RO
RO
29
13
reserved
0
0
Name
BA
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0
9
0
0x0
-
reserved
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Boot Alias
■
■
This bit is cleared by writing a 1 to this bit position.
When the BA bit is set, the boot alias is in effect and the ROM appears
at address 0x0. When the BA bit is clear, the Flash appears at address
0x0.
The device has ROM.
The first two words of the Flash memory contain 0xFFFF.FFFF.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
June 02, 2008
R/W1C
RO
BA
16
0
0
-
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