AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 8

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

Note that since we do not allow overlapped address and data tenures, we do not know whether the next
transfer is to the same SRAM page or not, so we cannot stream data (that is, 3-1-1-1/1-1-1-1/... cycles). This
requires much more logic and is left as an exercise for the reader.
A Þnal issue which must be handled is terminating an access. Burst SRAMÕs operate by streaming data into
or out of the chip on each clock edge after an initial setup sequence ( ADSC ), until instructed to stop. While
read operations can be ignored by forcing G high, write operations cannot be similarly controlled, so instead
a Òde-selectÓ cycle must be performed after each access. This is done by asserting ADSC without no chip
select asserted; when deselected, the SRAM will stop reading or writing data.
3.2 Flash Memory Controls
Flash memory devices use traditional OE , CS and WE signals to perform single-beat read and write cycles
(burst transfers are not permitted
PowerPC bus does not care if data is placed on ignored byte lanes during read cycles, it will be acceptable
to use OE in common for all ßash ROMs.
Write cycles require more care. Requiring the processor to perform 64-bit writes is unacceptable because it
is difÞcult (that is, requires the ßoating-point unit on the MPC devices) or impossible (on the non-ßoating-
point MPE devices) to do a 64-bit single-beat bus transfer. Thus, ßash devices must be fully-qualiÞed with
byte-enables during write cycles.
Using standard ßash devices will require the following control signals:
This gives a ßash memory architecture as shown in Figure 5.
1
may not be considered a big performance limitation.
8
This implies that the ROM space is non-cacheable; since Flash ROM is so much slower than SRAM, critical code should be copied to SRAM, so this
BWE(0Ð7)
FOE
FCS
BWE0
BWE2
BWE6
BWE4
FOE
FCS
Freescale Semiconductor, Inc.
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Active-low byte-write enables; if not asserted, the cycle is a read.
Active-low output enable; asserted for all read operations.
Active-low chip enable; asserted for all operations.
Minimal PowerPC System Design
Figure 5. Flash Memory Connections
1
), whether the data width of the device is 8-bits or 16-bits. Since the
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WE
OE
CS
WE
OE
CS
WE
OE
CS
WE
OE
CS
M29F800
(16-bit)
M29F800
(16-bit)
M29F800
(16-bit)
M29F800
(16-bit)
BYTE
BYTE
BYTE
BYTE
3.3V
3.3V
3.3V
3.3V
Remember:
3.3V Devices
ONLY!
MOTOROLA