AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 15

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
Note that the Òbytedec()Ó module examines the decoded write status (WE_L) but not CLAIM, so the byte
lane enables are asserted for all write cycles regardless of the activity of the CLAIM signal. This is
acceptable as long as the corresponding chip-select signals disable the attached memory and I/O devices,
which is true for the devices used.
The VHDL code for the Òbytedec()Ó module is lengthy but straightforward. The values are directly derived
from the data alignment tables in the processor user manuals, for example Table 8-3 and Table 8-4 of the
MPC750 RISC Microprocessor UserÕs Manual. Burst transfers enable all byte lanes, while all other
transfers enable only the byte lanes based upon the address and transfer size.
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-- BYTEDEC.VHD
--
-- BYTEDEC() is the portion of the MC which provides
--
--
--
--
-- Copyright 1998, by Motorola Inc.
-- All rights reserved.
--
-- Author:
-- Revision: 0.1
-- Date:
-- Notes:
--
--
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------
ENTITY BYTEDEC is
end; --PORT DEFINITION AND ENTITY
------------------------------------------------------------------------------------------------
ARCHITECTURE BEHAVIOR OF BYTEDEC is
SIGNAL be_L : std_logic_vector( 0 to 7 );
BEGIN
-- Convert transfer size and address into byte lane enables. Write masking
-- occurs later.
be_L(0) <= '0'
PORT(
individual byte write enabled for each byte lane, depending upon
the size and address of the transfer. If the cycle is a read cycle,
no outputs are asserted at all.
);
a
tsiz
tbst_L
we_L
bwe_L
Gary Milliorn
6/10/98
All logic is active low when appended with a "_L".
Passed speedwave check 6/10/98.
TSIZ(0Ð2)
A(29Ð31)
WHEN ( (tsiz = "001" and a = "000")
Freescale Semiconductor, Inc.
TBST
we_L
For More Information On This Product,
or (tsiz = "010" and a = "000")
or (tsiz = "100" and a = "000")
or (tsiz = "000" and a = "000")
or (tsiz = "011" and a = "000")
: in
: in
: in
: in
: buffer std_logic_vector( 0 to 7 )
Figure 10. Byte Write Enable Module
Minimal PowerPC System Design
3
3
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std_logic_vector( 29 to 31 ); -- stable 60X bus address
std_logic_vector( 0 to 2 );
std_logic;
std_logic;
bytedec()
-- byte lane enables (read or write).
8
-- byte
-- half-word
-- word
-- double-word
-- three-byte
-- current transfer size.
-- asserted if transfer is burst.
-- asserted if transfer is write.
-- byte lane write selects.
BWE(0Ð7)
15