AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 7

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
3.1 SRAM Memory Controls
The SRAM interface is centered around the controls necessary for a typical pipelined burst SRAM memory,
as used on the MPC750 back-side cache or various other PC systemÕs L2 cards. Flow-through SRAM
memories could also be used, but the timing for write operations would change. Since this is a simple
memory controller, it will be architected for only one type of SRAM. Most SRAM devices have numerous
controls which are not needed, leaving us with the following:
The memory controller must generate these signals for all SRAM transfers, whether single-beat or burst
transfers. ADSC and SE1 start the cycle by latching the address into the SRAM; these must be provided by
the memory controller at the same time. Since SE1 is asserted one clock after TS if the address matches an
SRAM space, the memory controller also asserts ADSC for memory cycles. The BWE signals
corresponding to the size of the transfer must be asserted if the cycle is a write cycle; otherwise, G must be
asserted to read in data (all byte lanes are driven and the processor selects the data from whichever byte lane
is needed).
The remaining signal is ADV , which must be asserted for three clock cycles if a burst transfer is selected;
otherwise, it remains high. Although the data rate could be throttled with ADV or G , this is not necessary
for the processor, so, to simplify the design, only fast SRAMs will be accommodated.
The remaining portion of the SRAM controller to specify is the initial access time. Most SRAMs available
today can decode an address within 10 ns from the address strobe ( ADSC ), so there is no need to delay
before beginning a transfer.
A(nÐ0)
ADSC
ADV
BWE(a-d)
G
SE1
Controller
Memory
MPC750
Figure 4. Pipelined Burst SRAM Memory Connections
TS
BWE(0Ð7)
Freescale Semiconductor, Inc.
ADSC
BAA
SOE
For More Information On This Product,
SCS
Memory address, including LSB for burst transfers and critical-word Þrst.
Addresses 0 and 1 are the LSBs and are used for burst transfer addresses.
Latches address for single-beat or burst transfers
Increments address for burst transfers
Active-low byte-write enables; if not asserted, the cycle is a burst read.
Active-low output enable; asserted for all read operations.
Active-low chip enable; asserted for all operations.
Minimal PowerPC System Design
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ADSC
ADV
SB(AÐD)
G
SE1
ADSC
ADV
SB(AÐD)
G
SE1
MCM69P737
MCM69P737
ADSP
ADSP
SGW
SGW
LBO
LBO
SE2
SE2
SE3
SE3
SW
SW
VDD
VDD
GND
GND
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