AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 24

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

The preceeding code was produced by a state machine compiler, so there are no comments and it is not very
readable. The code uses a Òone-hotÓ encoding (one register encodes each state), so each clock cycle the
registers are reloaded with the encoded next state calculations in a typical Moore machine fashion. The
remainder of the code computes the next state, and provides the encoded output. The code for calculating
the timing value (TIME) looks complicated because all four bits are calculated in one statement.
3.5.5 Memory Controller Module
The Þnal module is the memory controller itself, which simply interconnects the previous modules, and is
shown previously in Figure 8.
The VHDL code for this module is:
24
USE synth.vhdlsynth.all;
ENTITY CYCLER IS
END;
ARCHITECTURE BEHAVIOR OF CYCLER IS
BEGIN
END BEHAVIOR;
CONFIGURATION SHELL2_CYCLER OF CYCLER IS
END SHELL2_CYCLER;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-- MC.VHD
--
-- MC is an FPGA which implements a simple but fast MC for the PowerPC 60X/7XX
-- family of processors. The controller is described in detail in Application Note AN17XX,
-- "A minimal PowerPC System Design".
--
-- Most of MC is just a top-level interconnect of lower-level modules:
--
--
--
--
--
--
--
--
--
--
--
--
--
-- Copyright 1998, Motorola Inc.
-- All rights reserved.
--
-- Author:
-- Revision: 0.3
-- Date:
-- Notes:
--
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
PORT (CTIME : IN std_logic_vector (3 DOWNTO 0);
COMPONENT SHELL_CYCLER
END COMPONENT;
SHELL1_CYCLER : SHELL_CYCLER PORT MAP (CLK=>CLK,CLAIM_L=>CLAIM_L,CTIME0=>
FOR BEHAVIOR END FOR;
CLK,CLAIM_L,DOERR_L,RST_L,SCS_L,TBST_L,WE_L: IN std_logic;
AACK_L,ADSC_L,BAA_L,TA_L,TEA_L : OUT std_logic);
PORT (CLK,CLAIM_L,CTIME0,CTIME1,CTIME2,CTIME3,DOERR_L,RST_L,SCS_L,TBST_L,
CTIME(0),CTIME1=>CTIME(1),CTIME2=>CTIME(2),CTIME3=>CTIME(3),DOERR_L=>DOERR_L,
RST_L=>RST_L,SCS_L=>SCS_L,TBST_L=>TBST_L,WE_L=>WE_L,AACK_L=>AACK_L,ADSC_L=>
ADSC_L,BAA_L=>BAA_L,TA_L=>TA_L,TEA_L=>TEA_L);
ttdec
int
start
chipsel : provides chip select and output enables for devices depending
bytedec : provides byte-write enables for SRAM and Flash.
cycler
All logic is active low when appended with a "_L"
WE_L: IN std_logic;
AACK_L,ADSC_L,BAA_L,TA_L,TEA_L : OUT std_logic);
Gary Milliorn
6/21/98
: checks TT and asserts CLAIM or DOERR depending on whether the
: handles timing of assertion of AACK* and TA*, or of AACK* and TEA*,
: uses TT bits to separate cycles into handled and non-handled types.
: simple interrupt merge.
transfer will be handled or not.
upon the current address. Provides timing values for cycler to
use. Speculatively asserts ADSC*.
depending on CLAIM or DOERR status. Handles burst, single-beat
with various timings.
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
Go to: www.freescale.com
MOTOROLA