AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 17

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AN1769

Manufacturer Part Number
AN1769
Description
Designing a Minimal PowerPC System
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
MOTOROLA
The three-byte cycles arise from the need to handle misaligned transfers by breaking them into two separate
cycles; refer to the MPC603e and EC603e RISC Microprocessor UserÕs Manual or the MPC750 RISC
Microprocessor UserÕs Manual for details on this process. These cycles do not occur if unaligned transfers
do not occur. Since many C compilers do not generate such code, the lines for three-byte handling can be
deleted to simplify the controller and reduce gate count.
3.5.3 Chip Select
The chip-select module, shown in Figure 11, generates the four chip-select signals and selects the proper
time delay for accesses to memory (this information is used by the Òcycler()Ó module).
Table 5 shows the chip-select actions based upon the address.
The timer values in Table 5 have a constant overhead of three subtracted from the expected timer values.
This constant overhead is due to the start delay, the Þnal TA assertion, and one clock needed to detect a zero-
count on the timer. So for best performance, the actual timer values are offset by (-3). In examining chipsel(),
the SRAM chip select is found to be fairly straightforward; the other chip selects differ in that a 4-bit timer
value is generated to add delay to the assertion of TA.
00
01
10
11
END BEHAVIOR;
------------------------------------------------------------------------------------------------
A(0Ð1)
bwe_L(3) <= (be_L(3) or we_L);
bwe_L(4) <= (be_L(4) or we_L);
bwe_L(5) <= (be_L(5) or we_L);
bwe_L(6) <= (be_L(6) or we_L);
bwe_L(7) <= (be_L(7) or we_L);
High-speed SRAM array
High-speed I/O
Slow-speed I/O
Flash boot ROM
CLAIM_L
A(0Ð1)
I/O Area
WE_L
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
Table 5. Chip Select Encodings
Figure 11. Chip Select Module
2
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N/A
60 ns
180 ns
80 ns
Time (66 MHz)
chipsel()
N/A
4
12
6
Bus Clock Count
4
SCS
FCS
XCS(0Ð1)
CTIME(0Ð3)
SOE
FOE
XOE
N/A
1
9
3
Timer Value
17

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