AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 11

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
All other signals are either wired to the necessary state or are unused as described in Table 1. For example,
since the PowerPC bus is parked permanently, detecting BG, ABB, DBG and DBB are unnecessary. The
memory controller interface then requires a total of 35 I/O signals, well within the capacity of any modern
FPGA, leaving lots of I/O for additional functions.
3.5 Memory Controller Details
The remainder of Part 3, ÒMemory System Design,Ó describes the internal operations of the memory
controller as used on the Excimer reference board. The code is based upon synthesizable VHDL code, but
could be easily adapted to Verilog, and any of the several IC-speciÞc HDL variants that exist for Actel,
Altera, Lattice, Xilinx et. al.
Figure 8 shows the internal architecture of the memory controller module.
3.5.1 Start Detection Module
Upon receiving a TS, the memory controller must examine the TT(0Ð4) signals to determine the type of
cycle that will be performed. Of the 32 possible permutations, only those found in Table 4 are of interest:
TSIZ(0Ð2)
A(29Ð31)
TT(0Ð4)
A(0Ð1)
TBST
CLK
RST
TS
Freescale Semiconductor, Inc.
start()
For More Information On This Product,
Figure 8. Memory Controller Architecture
Minimal PowerPC System Design
Go to: www.freescale.com
WE_L
CLAIM_L
DOERR_L
bytedec()
chipsel()
CTIME(0Ð3)
cycler()
AACK
TEA
BAA
TA
BWE(0Ð7)
ADSC
XCS(0Ð1)
XOE
SCS
SOE
FCS
FOE
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