AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 20

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

The state machine switches from the IDLE state to the BEAT1 state on detection of any claimed burst cycle
(TBST_L and CLAIM_L asserted, which is only allowed for SRAM). This begins a four-beat burst transfer
with TA low for four clock cycles (the state machine clocks at the bus frequency, and so proceeds from
BEAT1 to BEAT4 automatically). In states BEAT1 through BEAT3, the BAA signal is asserted to cause the
burst SRAM devices to increment the address. This produces an SRAM access rate of 2-1-1-1 (excluding
the TS).
Alternately, if CLAIM_L is asserted but not TBST, and the cycle is for the SRAM (SCS_L asserted), then
this is a single-beat access to SRAM. While this could have been handled by the timer (say by presetting it
to 0001), the overhead of checking the timer costs additional cycles. By detecting SRAM single-beats
separately, fast access to SRAM is guaranteed (two clocks).
Otherwise, the cycle is either an error or a single-beat access to Flash or I/O. In the latter cases, only one
clock of TA is needed, but a lengthy delay may be needed to give the peripheral device time to complete the
access. For such devices, within the cycler() state-machine is an internal timer which is continually re-
loaded while in the IDLE state; in any other state, it counts downward. When the timer reaches zero and the
20
Moore Machine State Outputs
Vector Declarations
AACK_L =
ADSC_L = not ( (IDLE and !SCS_L and !CLAIM_L)
BAA_L =
TA_L =
TEA_L = not ( ERROR )
CTIME[] = 3:0
TIMER[] = 3:0
not (BEAT4 or ERROR)
not ( (BURST or BEAT1 or BEAT2)
not ( (BEAT1 or BEAT2 or BEAT3 or BEAT4)
or DESEL)
or (BEAT4 and !WE_L and !TBST_L)
or (!TBST_L and !WE_L)
or (BURST and !WE_L) )
TIMER <> "0000"
ERROR
!DOERR_L
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
TIMER £ TIMER Ð 1;
TIMER = CTIME;
!CLAIM_L &
Figure 13. Cycler() State Flow
SCS_L &
Go to: www.freescale.com
COUNT
COUNT
TBST_
Cycler - Milliorn 98SEP25
TIMER = "0000"
!RST_L
IDLE
CYCLER.DIA
!CLAIM_L &
SINGLE
!SCS_L &
TBST_
!CLAIM_L &
!SCS_L &
!TBST_I
DESEL
BURST
BEAT1
BEAT2
BEAT3
BEAT4
WE_L
!WE_L
MOTOROLA