AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 40

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

8.1 Merging Reset Signals
The COP port requires the ability to independently assert HRESET or TRST in order to fully control the
processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic. It is not possible to just wire the reset signals together, damage to the COP system or the target
system may occur.
The arrangement shown in Figure 29 allows the COP to independently assert HRESET or TRST, while
insuring that the target can drive HRESET as well. The pull-down resistor on TRST insures that the JTAG
scan chain is initialized during power-on if the COP is not attached; if it is, it is responsible for driving
TRST when needed.
40
7
8
9
10
11
12
13
14
15
16
Pins
TCK
PRESENT
TMS
N/A
SRESET
N/A
HRESET
N/A
CKSTPO
Ground
Signal
From Target
Board Reset
Sources
TCK
Optional
TMS
SRESET
HRESET
CKSTPO
Digital Ground
Connection
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6. COP Pin Definitions (Continued)
Minimal PowerPC System Design
HRESET
Figure 29. COP Reset Merging
All
All
All
All
All
All
603e, 603ev, 740, 750
All
Go to: www.freescale.com
Applicable Processor
COP Header
2KW
Add 10K pullup to VDD. May be used to
separate JTAG scan chains; see section
8.2.
Merge with on-board SRESET, if any.
Merge with on-board HRESET.
Key location; pin should be removed.
Add 10K pullup to VDD.
HRESET
TRST
PowerPC
Special
MOTOROLA