AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 37

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
6.4 Bypassing
A well-designed power supply will be quickly undermined if a poor bypassing system is used. Attention to
bypassing is essential to eliminate poor ground-return paths through the PCB and to help quell transient
noise and voltage drooping due to switching consideration.
High-frequency bypassing is provided by numerous 0.1 mF ceramic capacitors located near each power pin.
Only surface mount devices may be used, and preferably in the smallest package possible (0805 or 0508Ñ
with power connections on the ÔlongÕ side). Each capacitor should have a direct via to the power or ground
plane, with a short connection to the power pin.
On PowerPC devices in BGA packages, the solder pads connecting to power pins (balls) should be
connected directly to a power or ground plane with a via. Since there are no pins, the bypass capacitors
should surround the device on the bottom layer of the board. If placing components on the bottom of the
board is not allowed, the next most preferable placement is to surround the part as close as possible to the
BGA escape pattern.
In addition, a good design will include several ÒbulkÓ storage capacitors distributed around the PCB and
connected to the V
recharging of the smaller bypass capacitors, so the bulk capacitors should have a low equivalent series
resistance (ESR) rating to ensure the quick response time necessary. Each bulk capacitor should be at least
100 µF, and there should be one device for every 20 high-frequency capacitors (more if they cannot be
placed relatively close).
Part 7 Interrupts
The PowerPC processor has one standard interrupt signal (INT) that can be connected to an external
interrupt source if needed. This is in keeping with the RISC philosophy in which software manages
(optional) highly complex details and hardware aims to be fast. As long as the interrupting device is level-
sensitive, it can be wired directly to the processorÕs INT input (perhaps with an inverter, if necessary).
If extra interrupts are needed, the simplest manner is to merge all level-sensitive interrupts with a logic gate
as shown in Figure 26.
Software must poll all potential interrupting devices to determine which one (or more) has caused the
interrupt and clear it. This approach does not allow any priority among interrupts, nor can any interrupt be
masked unless the interrupting device provides a means to do so.
One way to quickly identify different interrupts is to assign them each an interrupt vector by reusing the
special-purpose interrupts SMI and MCP, as shown in Figure 27.
Level Sensitive
Interrupts
DD
and OV
Freescale Semiconductor, Inc.
INT0
INT1
INT2
For More Information On This Product,
DD
...
Figure 26. Simple Interrupt Merging
power planes. These capacitors provide local energy storage for quick
Minimal PowerPC System Design
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INT
PowerPC
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