LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 70

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
70
Reset
Reset
Type
Type
Bit/Field
31:6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
RO
RO
30
14
0
0
reserved
Name
WDT
LDO
BOR
POR
EXT
SW
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
reserved
RO
RO
26
10
0
0
Reset
0
-
-
-
-
-
-
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
When set, indicates a software reset is the cause of the reset event.
When set, indicates a watchdog reset is the cause of the reset event.
When set, indicates a brown-out reset is the cause of the reset event.
When set, indicates a power-on reset is the cause of the reset event.
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
LDO
R/W
RO
21
0
5
-
R/W
RO
SW
20
0
4
-
WDT
R/W
RO
19
0
3
-
BOR
R/W
RO
18
0
2
-
June 14, 2007
POR
R/W
RO
17
0
1
-
EXT
R/W
RO
16
0
0
-