LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 21

no-image

LM3S1150-IQC50-A1

Manufacturer Part Number
LM3S1150-IQC50-A1
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
June 14, 2007
Internal Memory
General-Purpose Timers
Hardware-division and single-cycle-multiplication
Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
34 interrupts with eight priority levels
Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
Unaligned data access, enabling data to be efficiently packed into memory
Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
64 KB single-cycle flash
16 KB single-cycle SRAM
Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timer/counters. Each GPTM can be configured to operate independently as timers or event
counters (eight total) as a single 32-bit timer (four total), as one 32-bit Real-Time Clock (RTC)
to event capture, or for Pulse Width Modulation (PWM)
32-bit Timer modes
16-bit Timer modes
16-bit Input Capture modes
User-managed flash block protection on a 2-KB block basis
User-managed flash data programming
User-defined and managed flash-protection block
Programmable one-shot timer
Programmable periodic timer
Real-Time Clock when using an external 32.768-KHz clock as the input
User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
General-purpose timer function with an 8-bit prescaler
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
Luminary Micro Confidential-Advance Product Information
LM3S1150 Microcontroller
21

Related parts for LM3S1150-IQC50-A1