LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 426

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LM3S1150-IQC50-A1

Manufacturer Part Number
LM3S1150-IQC50-A1
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
Signal Tables
426
Pin Number
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Luminary Micro Confidential-Advance Product Information
Pin Name
I2C0SCL
I2C0SDA
SSI1Clk
SSI1Fss
SSI1Rx
SSI1Tx
CMOD0
CMOD1
SWDIO
SWCLK
CCP0
CCP2
PWM3
PWM2
PB0
PB1
VDD
GND
PB2
PB3
PE0
PE1
PE2
PE3
PC3
SWO
TDO
PC2
TDI
PC1
TMS
PC0
TCK
VDD
GND
PH1
PH0
GND
NC
NC
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
-
-
-
-
-
-
-
I
I
I
I
Buffer Type
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
OD
-
-
Description
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
Capture/Compare/PWM 0
GPIO port B bit 0
Capture/Compare/PWM 2
GPIO port B bit 1
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
I2C module 0 clock
GPIO port B bit 2
I2C module 0 data
GPIO port B bit 3
GPIO port E bit 0
SSI module 1 clock
GPIO port E bit 1
SSI module 1 frame
GPIO port E bit 2
SSI module 1 receive
GPIO port E bit 3
SSI module 1 transmit
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
GPIO port C bit 3
JTAG TDO and SWO
JTAG TDO and SWO
GPIO port C bit 2
JTAG TDI
GPIO port C bit 1
JTAG TMS and SWDIO
JTAG TMS and SWDIO
GPIO port C bit 0
JTAG/SWD CLK
JTAG/SWD CLK
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
No connect
No connect
GPIO port H bit 1
PWM 3
GPIO port H bit 0
PWM 2
Ground reference for logic and I/O pins.
June 14, 2007

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